The present disclosure relates generally to semiconductor devices, and more specifically, relates to semiconductor structures, including three-dimensional (3D) gate-all-around (GAA) vertical gate (VG) structures in semiconductor devices, and methods of fabricating such semiconductor structures and devices.
There is an ever growing need by semiconductor device manufacturers to further shrink the critical dimensions of semiconductor structures and devices, to achieve greater storage capacity in smaller areas, and to do so at lower costs per bit. Three-dimensional (3D) semiconductor devices using, for example, thin film transistor (TFT) techniques, charge trapping memory techniques, and cross-point array techniques, have been increasingly applied to achieve the above needs by semiconductor manufacturers. Recent developments in semiconductor technology have included the fabrication of vertical structures in the form of 3D vertical channel (VC) NAND structures or 3D vertical gate (VG) NAND structures.